The present invention relates generally to cascaded delta-sigma modulators, and more particularly to delta-sigma modulators that have flat transfer characteristics and reduced power dissipation, and which require reduced amounts of integrated chip area, and which are immune to the nonlinearity of the operational amplifier used to implement the integrator.
FIG. 1A is a block diagram of a conventional second order delta-sigma modulator 1A that is commonly used in cascaded delta-sigma modulators. Sometimes it is advantageous to cascade delta-sigma modulators. For example, cascading two second order delta-sigma modulators may provide a fourth-order delta-sigma modulator which is more stable than a traditional single stage fourth order delta-sigma modulator.
Second order delta-sigma modulator 1A in Prior Art FIG. 1A includes an analog adder 2 that receives an analog input signal X(z) and a feedback signal V9A on conductor 9A. The input of delta-sigma modulator 1A can be represented by x(t) in the time domain and by X(z) in the frequency domain, and similarly, the output of delta-sigma modulator 1A can be represented by y(t) in the time domain and by Y(z) in the frequency domain. The output of adder 2 is coupled to the input of a conventional switched capacitor integrator 3. The details of switched capacitor integrator 3 together with adder 2 are shown in FIG. 1B. The output 3A of integrator 3 is connected to the (+) input of an analog adder 4, the (−) input of which is coupled to the output of an analog gain block 5, more generally referred to herein as gain block 5, which actually is implemented by suitably sizing the capacitors in Prior Art FIG. 1B, wherein the gain of 2 is not formed by a separate amplifier circuit but instead is accomplished by making the capacitance Cin2 equal to twice the capacitance Cin1 in the circuit of FIG. 1B as it is utilized in implementing adder 4 and integrator 6. The output 4A of adder 4 is connected to the input of integrator 6. The output 6A of integrator 6 is coupled to the input of an A/D (analog to digital converter) or quantizer 7, which can be thought of as having an input which represents a quantization noise e(t), which in the frequency domain is represented by E(z). The output of A/D or quantizer 7 can be a one-bit or multi-bit digital output signal Y(z), which is applied to the input of a D/A (digital to analog converter) 9, the output 9A of which produces the feedback signal V9A applied to the input of gain block 5 and the (−) input of adder 2.
The frequency domain transfer characteristic of the second order delta-sigma modulator 1A is given byY(Z)=Z−2X(z)+(1z−1)2E(z),  Eq. (1)wherein the variable “z” is a frequency-based transform variable. The outputs of first integrator 3 and second integrator 6 include input-dependant signal components. The transfer characteristic with respect to the signal on conductor 3A is indicated by the expression z−1(1+z−1)X(z)+z−(1−z−1)E(z). This expression shows that the signal on conductor 3A is a function of the input signal X(z) and the quantization noise E (z). This is undesirable because the output signal swing of integrator 3 is dependent on the level of the input signal X(z). Any nonlinearity in the operational amplifier of integrator 3 produces distortion in the delta-sigma modulator output signal Y(z). Even though the quantization noise E(z) could be input related, the input-related term is high-pass filtered at the output of integrator 3 due to the (1−z−1) term in Equation (1). The second order delta-sigma modulator 1A of FIG. 1A is very sensitive to non-linearity of the operational amplifier 11C (shown in subsequently described FIG. 1B) in integrator 3. Due to the limited output swing of the operational amplifier, the integrator capacitors Cint (shown in FIG. 1B) are quite large for delta-sigma modulator 1A in FIG. 1A and therefore require a substantial amount of integrated circuit chip area. Consequently, a considerable amount of power is required for integrators 3 to achieve fast signal settling.
Referring next to FIG. 1B, integrator 3 in combination with adder 2 in FIG. 1A can be implemented by a conventional switched-capacitor integrator, including an upper switched capacitor circuit 11A, which receives the differential input signal x(t), which is represented by X(z) in the frequency domain, and an operational amplifier 11C with to integrating capacitors Cint. Adder 2 is represented by a lower switched capacitor circuit 11B which receives the time domain feedback signal v9(t) on conductor 9A. Upper and lower switched-capacitor circuits 11A and 11B along with the corresponding (+) and (−) outputs of switched capacitor circuits 11A and 11B which are connected to the (+) and (−) inputs as shown, respectively, of operational amplifier 11C, perform the analog summing represented by analog summer 2 in FIG. 1A (and also in the other drawings herein). The differential output of operational amplifier 11C produces the time domain signal v3A(t).
FIG. 2 shows a conventional cascaded delta-sigma modulator 1B including two of the second order delta-sigma modulators 1A shown in FIG. 1A cascaded together. The upper delta-sigma modulator 1A-1 receives the input signal X(z). The output 9A of D/A 9 is connected to the (−) input of an analog adder 17, the (+) input of which is connected to the output 6A of integrator 6 of upper delta-sigma modulator 1A-1. This subtraction results in only quantization noise E1(z) being fed into the second stage 1A-2. (In the prior art cascaded delta-sigma modulators, the subtraction by adder 17 results in only E1(z) being fed into second stage 1A-2.) The output 17A of adder 17 is connected to the input of an interstage gain block 38 having a gain g. The output of gain block 38 is connected to the input of lower delta-sigma modulator 1A-2, which is identical to upper delta-sigma modulator 1A-1. Interstage gain block 38 ensurers that lower delta-sigma modulator 1A-2 does not saturate.
The outputs 7A of delta-sigma modulators 1A-1 and 1A-2 in FIG. 2 are connected to an all-digital error-cancellation circuit 12 (also referred to as “merging block 12”), which operates in the digital domain to cancel the quantization noise E1(z). The output of upper delta-sigma modulator 1A-1 is connected to the input of a digital delay block 13 of error cancellation circuit 12. The output of digital delay block 13 is connected to a (+) input of a digital adder 14. The output of lower delta-sigma modulator 1A-2 is connected to the input of a digital gain block 40 having a gain 1/g, in order to scale back the effect of interstage gain block 38 on the amplitude of the output of lower delta-sigma modulator 1A-2. The output of digital gain block 40 is connected to a digital block 16 with a transfer function (1−z−1)2. The output of digital block element 16 is coupled to another (+) input of digital adder 14, the output of which produces the output signal Y(z) of cascaded delta-sigma modulator 1B.
Cascading the two second order delta-sigma modulators 1A-1 and 1A-2 in this manner causes fourth-order delta-sigma modulator 1B to be unconditionally stable compared to a traditional single-stage fourth order delta-sigma modulator.
The transfer characteristic of cascaded delta-sigma modulator 1B of FIG. 2 is given by
                                                                        Y                ⁡                                  (                  z                  )                                            =                            ⁢                                                                    [                                                                                            z                                                      -                            2                                                                          ⁢                                                  X                          ⁡                                                      (                            z                            )                                                                                              +                                                                                                    (                                                          1                              -                                                              z                                                                  -                                  1                                                                                                                      )                                                    2                                                ⁢                                                                              E                            1                                                    ⁡                                                      (                            z                            )                                                                                                                ]                                    ⁢                                      z                                          -                      2                                                                      +                                                                                                      ⁢                                                [                                                                                    z                                                  -                          2                                                                    ⁡                                              (                                                                              -                                                                                          E                                1                                                            ⁡                                                              (                                z                                )                                                                                                              ⁢                          g                                                )                                                              +                                                                                            (                                                      1                            -                                                          z                                                              -                                1                                                                                                              )                                                2                                            ⁢                                                                        E                          2                                                ⁡                                                  (                          z                          )                                                                                                      ]                                ⁢                                                                            (                                              1                        -                                                  z                                                      -                            1                                                                                              )                                        2                                    /                  g                                                                                                        =                            ⁢                                                                    z                                          -                      4                                                        ⁢                                      X                    ⁡                                          (                      z                      )                                                                      +                                                                            (                                              1                        -                                                  z                                                      -                            1                                                                                              )                                        4                                    ⁢                                                                                    E                        2                                            ⁡                                              (                        z                        )                                                              /                                          g                      .                                                                                                                              Eq        .                                  ⁢                  (          2          )                    Equation (2) shows that cascaded delta-sigma modulator 1B is a fourth order delta-sigma modulator with quantization noise E1(z) canceled in the error-cancellation circuits, and the input transfer function is flat.
FIG. 3 shows a conventional low distortion second order delta-sigma modulator 1C that sometimes is used in cascaded delta-sigma modulators. Its transfer characteristic is given byY(z)=X(z)+(1−z−1)2E(z).  Eq. (3)The transfer characteristic respect to the signal on conductor 3A in FIG. 3 is indicated by the expression −z−1(1−z−1)E(z). In delta-sigma modulator 1C, the effective transfer characteristics at the output 3A of integrator 3 has only “E(z)” quantization noise terms. Even though the quantization noise E(z) could be input related, the input-related term is high-pass filtered at the output of integrator 3 due to the (1−z−1) term in the foregoing expression. Therefore, delta-sigma modulator 1C of FIG. 3 is more immune to non-linearity of the operational amplifiers of integrators 3. Furthermore, the output swing of integrator 3 is very stable for different levels of the input signal X(z). The integrator capacitors Cint (FIG. 1B) do not need to be as large as in the above mentioned delta-sigma modulators of FIGS. 1A and 2, and consequently less power is required to achieve acceptable integrator signal settling.
However, delta-sigma modulator 1C requires a feed-forward path from the input signal X(z) to the input of adder 4 ahead of A/D or quantizer 7. As will be readily understood by those skilled in the art, this feed-forward path may cause a “kick-back” effect on the input signal X(z), causing signal distortion as a result of the summation of three signals being provided by adder 4 to the input of A/D or quantizer 7. Typically, the actual implementation of adder 4 includes a passive network wherein the two signals including integrator output 6A and the output 5A of gain block 5 can cause the above-mentioned kick-back effect which distorts input signal X(z). The distorted input signal X(z) then is operated on by the delta-sigma modulator, thereby increasing distortion in the output signal Y(z).
FIG. 4 shows another low distortion second order delta-sigma modulator 10A which has several advantages over the above mentioned prior art second-order delta-sigma modulators. Second order delta-sigma modulator 10A of FIG. 4 includes an analog adder 2 that receives analog input signal X(z) and a feedback signal on conductor 9A. The output of adder 2 is coupled to the input of switched-capacitor integrator 3. (FIG. 1B shows a preferred implementation of adder 2 and integrator 3.) The output 3A of integrator 3 is coupled to the input of a second integrator 6 which can be identical to integrator 3, and also is connected to the input of an gain block 5 having a gain equal to 2. The output 6A of integrator 6 is connected to a (+) input of an analog adder 4, another (+) input of which is coupled to the output of gain block 5. The output of adder 4 is connected to the input of A/D or quantizer 7, which can be thought of as having an input which represents a quantization noise E(z). The output of A/D or quantizer 7 can be a one-bit or multi-bit digital output signal Y, which is applied to the input of a D/A converter 9. The output of D/A 9 produces the feedback signal V9A applied to the input of gain block 5 and the (−) input of adder 2. Note that low distortion second order delta-sigma modulator 10A in FIG. 4 is nearly identical to low distortion second order delta-sigma modulator 1C in FIG. 3, except that the feed-forward path in FIG. 3 from X(z) to adder 4 is omitted in FIG. 4. Therefore, delta-sigma modulator 10A avoids the previously described kick-back problem.
The transfer characteristic of delta-sigma modulator 10A is given by
                                                                        Y                ⁡                                  (                  z                  )                                            =                                                                                          z                                              -                        1                                                              ⁡                                          (                                              2                        -                                                  z                                                      -                            1                                                                                              )                                                        ⁢                                      X                    ⁡                                          (                      z                      )                                                                      +                                                                            (                                              1                        -                                                  z                                                      -                            1                                                                                              )                                        2                                    ⁢                                      E                    ⁡                                          (                      z                      )                                                                                                                                              =                                                X                  ⁡                                      (                    z                    )                                                  +                                                                            (                                              1                        -                                                  z                                                      -                            1                                                                                              )                                        2                                    ⁢                                                            (                                                                        E                          ⁡                                                      (                            z                            )                                                                          -                                                  X                          ⁡                                                      (                            z                            )                                                                                              )                                        .                                                                                                          Eq        .                                  ⁢                  (          4          )                    
z−1 represents a time delay. Integrator 3 is a “delayed” integrator. The delay involved arises as a result of the time durations associated with the two clock signals shown in the switched-capacitor implementation of FIG. 1B. The transfer characteristic with respect to the signal on conductor 3A is indicated by the expression −z−1(1−z−1)(E(z)−X(z)), wherein the term (1−z−1) represents a high pass filter. The base band of interest is very low compared to the over-sampling frequency of the switched capacitor integrators 3, and the sampling frequency is much greater than the Nyquist rate. Even though the transfer characteristic at conductor 3A has an X(z) term, it is greatly reduced because of the high pass filtering.
The output of the first integrator 3 only includes a high pass filtered input signal, which is likely to be negligible. This provides an advantage of low distortion second order delta-sigma modulator 10A of FIG. 4 over the low distortion delta-sigma modulator 1C of FIG. 3. This is in addition to the advantage that the kick-back effect is avoided and because no feed-forward path is required. However, the input-output transfer function of low distortion second-order delta-sigma modulator 10A, indicated by Equation (4), is not flat. Therefore, the correction block with transfer function 1/(2−z−1) needs to be added in the digital domain to cancel the “drooping” caused by the (2−z−1) term in Equation (4). (The settling in error cancellation circuit 12 could be an issue because it is an IIR (infinite impulse response) filter, since IIR filters characteristically have slow settling.)
The performance of low distortion second order delta-sigma modulator 10A of FIG. 4 is fairly similar to that of delta-sigma modulator 1C of FIG. 3, except there is none of the above mentioned kick-back problem in the circuit of FIG. 4. Also, the transfer function of delta-sigma modulator 1C of FIG. 4 is not flat. Since its transfer function is not flat, second order delta-sigma modulator 10A of Prior Art FIG. 4 would not ordinarily be considered as a practical option for use in a cascaded delta-sigma modulator circuit.
Thus, there is an unmet need for a cascaded delta-sigma modulator that has a flat transfer characteristic and reduced power dissipation, which requires reduced amounts of integrated chip area, and which is immune to nonlinearity of the operational amplifier used to implement the integrator.
There also is an unmet need for a cascaded delta-sigma modulator which has a flat transfer characteristic and reduced power dissipation, which is immune to nonlinearity of the operational amplifier used to implement the integrator, and which requires reduced amounts of integrated chip area even though a delta-sigma modulator therein has a transfer characteristic which is not flat.
There also is an unmet need for a cascaded delta-sigma modulator which avoids distortion due to kick-back caused by a feed-forward signal path in a delta-sigma modulator therein.